1. Field of the Invention
The present invention generally relates to semiconductor circuits, and specifically to a method for manufacturing a three-dimensional circuit apparatus.
2. Description of the Prior Art
Semiconductor circuits are being increasingly designed wherein integrated circuits of various technologies are combined. Thus, for example, CMOS memories are combined with bipolar processors and sensor modules are combined with logic modules. The integrated circuits are thereby usually arranged side-by-side on printed circuit boards. The integrated circuits contact one another via metal tracks.
These different integrated circuits are to be combined in a chip housing to achieve an increase in the packing density and a shortening of the connecting paths. The substrates that contain integrated circuits and that can be composed of different substrate materials and/or can be fabricated in different technologies are thereby respectively ground down to a few 10 .mu.m and are arranged as stacks. Contacts passing through the substrates must be fashioned in vertical direction. Viewed from the outside, such a component stack looks like a new semiconductor module. A standard housing having a reduced number of terminals can be used, even though the component stack has an enhanced functionality.
Three-Dimensional ICs Project (Fiscal 1981-1990) Research and Development Association for Future Electron. Dev., FED, Tokyo, 1991, Chapter 2.1, discloses a method in which vertical contacts can be realized between substrates arranged above one another in a stack. In a known method, contacts between an upper substrate and a lower substrate that are arranged immediately above one another and adjacent to one another in the stacks are produced. Tungsten pins having a cross section of approximately 3.times.3 .mu.m.sup.2 are formed on the upper side of the lower substrate. These tungsten pins project 1-2 .mu.m from the upper side of the lower substrate. Large-area depressions that have dimensions of approximately 20.times.20 .mu.m.sup.2 are produced at a corresponding location of the underside of the upper substrate, these being filled with an Au/In alloy. When the upper substrate and the lower substrate are stacked on top of one another, the tungsten pins penetrate into these filled depressions. They are soldered at 300.degree.-400.degree. C. A layer of polyimide as a glue is applied to the upper side of the lower substrate and to the underside of the upper substrate to compensate for surface topographies and to produce an additional, mechanical connection between the upper substrate and the lower substrate.
The upper side of the upper substrate has a stabilizing carrier plate glued onto it for producing the depressions at the underside of the upper substrate. Subsequently, the upper substrate is ground at the underside. An additional wiring level is subsequently produced at the underside, which is in communication with a metallization level of the circuit. The additional wiring level is covered with a polyimide layer wherein the depressions that are filled with Au/In are produced. The depressions thereby extend to the additional wiring level. These process steps lead to substantial stresses that can cause the thin substrate to warp or to even break where the carrier plate is not sufficient to meet these demands.
The tungsten pins are deposited on the upper side of the lower substrate at temperatures around 400.degree. C.-500.degree. C. When the pins cool, the lower substrate is placed under high stresses that attack at points in the substrate. Stress cracks can thereby occur with sensitive substrate materials such as, for example, GaAs or InP.
When soldering the upper substrate to the lower substrate, lateral shifts between the depressions and the tungsten pins occur, since the two substrates have different coefficients of expansion. So that tungsten pins and depressions allocated to one another meet one another despite these shifts, the alignment tolerances and, thus, the dimensions of the depressions must be correspondingly enlarged. During cooling after soldering, these shifts lead to great transfer forces that act on the tungsten pins can lead to the contacts being cut off.
In order to reduce the mechanical stress on the substrates to a bearable degree, the tungsten pins cannot be too densely arranged and cannot be too deeply introduced into the substrate material. The tungsten pins therefore contribute little to the elimination of waste heat from the circuits and components in the substrate.
To form complex component stacks more than two substrates are soldered on top of one another. A detachment of the contacts when soldering additional substrates can only be avoided in the known method by using Au/In alloys with a decreasing melting temperature from level to level. The repeated heating of an alloy to just below the melting point, however, leads to a modification of the crystal structure and a degradation of the contacts.